1. Field of Invention
The present invention relates to a multipurpose half bridge signal output circuit; particularly, it relates to such multipurpose half bridge signal output circuit capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode through different connection relationships among two output pins and one external resistor.
2. Description of Related Art
Please refer to FIG. 1, which shows a schematic diagram of a conventional half bridge signal output circuit capable of operating under a charge sharing mode. As shown in FIG. 1, the conventional half bridge signal output circuit 10 is designed for operating under a charge sharing mode and it comprises plural half bridge signal output unit sets. Each of the half bridge signal output unit sets comprises a first half bridge signal output unit 101A and a second half bridge signal output unit 101B. For example, as shown in FIG. 1, two half bridge signal output unit sets are illustrated. Each first half bridge signal output unit 101A comprises a first high voltage switch P1, a first low voltage switch N1, a first capacitor C1 and a voltage adjustment switch MD. The first high voltage switch P1 has one end coupled to a high voltage source VGH and another end coupled to a first switching node LX1. The first low voltage switch N1 has one end coupled to a low voltage source VGL and another end coupled to the first switching node LX1. The first capacitor C1 has one end coupled to a first output terminal CKV1 (or CKV2). The voltage adjustment switch MD has one end coupled to the first output terminal CKV1 (or CKV2) and another end coupled to a first output pin CKVCS1 (or CKVCS2). Each second half bridge signal output unit 101B comprises a second high voltage switch P2, a second low voltage switch N2 and a second capacitor C2. The second high voltage switch P2 has one end coupled to the high voltage source VGH and another end coupled to a second switching node LX2. The second low voltage switch N2 has one end coupled to the low voltage source VGL and another end coupled to the second switching node LX2. The second capacitor C2 has one end coupled to a second output terminal CKVB1 (or CKVB2). The second output terminal CKVB1 (or CKVB2) has one end coupled to the second capacitor C2 and another end coupled to the second output pin CKVBCS1 (or CKVBCS2). The first output pin CKVCS1 is coupled to the second output pin CKVBCS1 through a resistor R1. The first output pin CKVCS2 is coupled to the second output pin CKVBCS2 through a resistor R2.
The following paragraph takes the first output voltage CKV1 and the second output voltage CKVB1 for example to explain how the conventional half bridge signal output circuit 10 operates under the charge sharing mode. Under normal operation, in one case, the first half bridge signal output unit 101A turns ON the first high voltage switch P1 and turns OFF the first low voltage switch N1, thereby outputting the first output voltage CKV1 having a voltage level equal to the high voltage source VGH. In the meantime, the second half bridge signal output unit 101B turns OFF the second high voltage switch P2 and turns ON the second low voltage switch N2, thereby outputting the second output voltage CKVB1 having a voltage level equal to the low voltage source VGL. Or, in another case, the first half bridge signal output unit 101A turns OFF the first high voltage switch P1 and turns ON the first low voltage switch N1, thereby outputting the first output voltage CKV1 having a voltage level equal to the low voltage source VGL. In the meantime, the second half bridge signal output unit 101B turns ON the second high voltage switch P2 and turns OFF the second low voltage switch N2, thereby outputting the second output voltage CKVB1 having a voltage level equal to the high voltage source VGH. In summary, the first output voltage CKV1 and the second output voltage CKVB1 are complementary to each other. When the conventional half bridge signal output circuit 10 operates under the charge sharing mode, the control signals (not shown) for controlling the first output voltage CKV1 and the second output voltage CKVB1 will turn ON the voltage adjustment switch MD of the first half bridge signal output unit 101A, and turn OFF the first high voltage switch P1, the first low voltage switch N1, the second high voltage switch P2 and the second low voltage switch N2. As a result, the two output terminals (i.e., the first output voltage CKV1 and the second output voltage CKVB1) are connected with each other through the resistor R1 and therefore can share charges. The details as to how charges are shared under the charge sharing mode are well known to those skilled in the art, which are not redundantly repeated here. The resistor R1 is for tuning the speed and slope of the charge sharing operation. That is, the charge sharing speed and the charge sharing slope can be adjusted by adjusting the resistance of the resistor R1.
In this prior art, in order to perform charge sharing function, it is required to provide one resistor and a pair of output pins (i.e., the first output pin CKVCS1 or CKVCS2 and the second output pin CKVBCS1 or CKVBCS2) for each of the half bridge signal output unit sets (i.e., each set of first half bridge signal output unit 101A and second half bridge signal output unit 101B). If there are more half bridge signal output unit sets, more resistors and output pins are required.
Please refer to FIG. 2, which shows a schematic diagram of a conventional half bridge signal output circuit capable of operating under a gate pulsing modulation mode. As shown in FIG. 2, the conventional half bridge signal output circuit 20 is designed for operating under a gate pulsing modulation mode and it comprises plural half bridge signal output units 201˜204. For example, as shown in FIG. 2, four half bridge signal output units 201˜204 are illustrated. Each of the half bridge signal output units 201˜204 comprises a high voltage switch P1, a low voltage switch N1, a capacitor C1 and a voltage adjustment switch RE1 (or RE2˜RE4). The high voltage switch P1 has one end coupled to a high voltage source VGH and another end coupled to a switching node LX1. The low voltage switch N1 has one end coupled to a low voltage source VGL and another end coupled to the switching node LX1. The capacitor C1 has one end coupled to an output terminal LSOUT1 (or LSOUT2˜LSOUT4). The voltage adjustment switch RE1 (or RE2˜RE4) has one end coupled to the output terminal LSOUT1 (or LSOUT2˜LSOUT4) and another end coupled to one single output pin RE. There is one resistor R1 disposed outside the conventional half bridge signal output circuit 20. The resistor R1 has one end coupled to the output pin RE and another end coupled to a middle voltage level between the high voltage source VGH and the low voltage source VGL. When the high voltage source VGH is a positive voltage and the low voltage source VGL is a negative voltage, the middle voltage level is for example the ground level.
The following paragraph takes the output voltage LSOUT1 for example to explain how the conventional half bridge signal output circuit 20 operates under the gate pulsing modulation mode. Under normal operation, in one case, the half bridge signal output unit 201 turns ON the high voltage switch P1 and turns OFF the low voltage switch N1, thereby outputting the output voltage LSOUT1 having a voltage level equal to the high voltage source VGH. Or, in another case, the half bridge signal output unit 201 turns OFF the high voltage switch P1 and turns ON the low voltage switch N1, thereby outputting the output voltage LSOUT1 having a voltage level equal to the low voltage source VGL. When it is required for the output voltage LSOUT1 to switch between the high level and the low level, the half bridge signal output unit 201 will first control the output voltage LSOUT1 to reach a middle level between the high level and the low level, and then control the output voltage LSOUT1 to switch to its target level. This is the so-called “gate pulsing modulation”. When the conventional half bridge signal output circuit 20 operates under the gate pulsing modulation mode, the control signals (not shown) for controlling the output voltage LSOUT1 will turn ON the voltage adjustment switch RE1 of the half bridge signal output unit 201 and turn OFF the high voltage switch P1 and the low voltage switch N1 of the half bridge signal output unit 201. In the meantime, the control signals (not shown) for the other output voltages LSOUT2˜LSOUT4 will turn OFF the voltage adjustment switch RE2˜RE4 of the half bridge signal output unit 202˜204. Thus, the output voltage LSOUT1 first reaches the middle voltage level (e.g., the ground level). After that, the voltage adjustment switch RE1 is turned OFF and the high voltage switch P1 or the low voltage switch N1 of the half bridge signal output unit 201 is turned ON, so that the output voltage LSOUT1 will switch to its target level. The details as to how to perform gate pulsing modulation are well known to those skilled in the art, which are not redundantly repeated here. The resistor R1 is for tuning the speed and the slope of the gate pulsing modulation. That is, the speed and the slope of the gate pulsing modulation can be adjusted by adjusting the resistance of the resistor R1.
The drawback of the two above-mentioned prior art circuits is that: they can perform only one single function. The prior art of FIG. 1 can only perform charging sharing operation but cannot perform gate pulsing modulation operation. The prior art of FIG. 2 can only perform gate pulsing modulation operation but cannot perform charging sharing operation.
In view of the above, to overcome the drawbacks in the prior art, the present invention proposes a multipurpose half bridge signal output circuit capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode through different connection relationships among two output pins and one external resistor.